Due to the ever increasing demand for cheaper, faster, more complex integrated circuit (IC) devices, IC manufacturers are replacing embedded memories based on standard planar transistor technologies with Fin Field Effect Transistor (FinFET) memories. The phrase “embedded memory” refers herein to on-chip (integrated) electronic memory devices that support a System-on-Chip (SoC) or other IC device's logic core (e.g., one or more microprocessors, a graphics processing unit (GPU), etc.). High-performance embedded memory arrays are a key component in modern SoC devices because their integration with the logic core on the same semiconductor (e.g., silicon) chip reduces both device sizes and data transfer delays, thereby facilitating lower manufacturing prices and higher processing speeds. Most conventional embedded memory arrays produced using well-established semiconductor fabrication technologies (e.g., with minimum features sizes of 28 nm or more) were implemented using planar static-random-access-memory (SRAM) technology, such as that shown and described below with reference to FIG. 12. In SoCs produced using more recently developed semiconductor fabrication technologies (e.g., those produced using semiconductor fabrication technologies with minimum features sizes of 22 nm or smaller) utilize embedded memories in which conventional planar SRAMs are replaced with FinFETs, such as those shown and described below with reference to FIGS. 13A and 13B. As explained below, FinFET architectures are better suited than planar SRAM architectures for smaller fabrication process feature sizes.
FIG. 12 shows a conventional planar SRAM cell in which a gate voltage applied to a doped polycrystalline silicon gate structure (Gate) controls channel current flow (indicated by the arrow from a source region (S) to a drain region (D)) through a channel region of a silicon substrate residing under the gate structure. The conventional planar SRAM architecture works well when the length of the channel under the gate (i.e., measured in the direction of the arrow in FIG. 10) is sufficiently large, but encounters short-channel effects when the channel is too short and too deep for the gate structure to control it properly, whereby a leakage current flows between the source and drain regions even when the gate is maintained at an “off” potential (i.e., the FET remains at least partially “on” at all times), which causes very high static power dissipation. This is the major process motivation for moving away from planar FET architectures as advances in semiconductor fabrication processes provide minimum features sizes of 22 nm and smaller.
FIGS. 13A and 13B show a single-fin FinFET cell and a multiple-fin FinFET cell, respectively. Referring to FIG. 13A, the single fin is formed by a thin silicon structure that extends upward from the silicon substrate and passes through the polycrystalline silicon gate structure (i.e., such that the gate material contacts both side and upper surfaces of the fin). The portion of the fin that passes through the gate structure forms the FinFET's channel. Because the channel is substantially entirely surrounded by the gate structure, current through the channel (indicated by the arrow) is well-controlled, and leakage is much lower than that experienced by planar SRAM FETs for a given channel length. The FinFET architecture also facilitates using two or more fins (e.g., three, as illustrated in FIG. 13B) to better control current flow at lower operating voltages, which enables FinFET embedded memories to function using lower operating voltages than those required by planar FET memories, which in turn reduces power consumption. Accordingly, as minimum features sizes move below 22 nm, FinFET cells have replaced SRAM FETs as the preferred embedded memory technology at least because of their lower leakage, but also because FinFETs are considered more power efficient than planar FETs.
Like any IP block-based circuit of a SoC or other fabricated IC device, all embedded memory arrays need to be tested before use. But unlike many other IP blocks that perform logic functions, memory testing does not involve a simple pass/fail process. Memories are typically designed with redundant rows and columns that can be used in place of faulty primary rows/columns having process-related defects, so memory testing typically involves identifying faulty primary rows/columns, and reconfiguring the embedded memory array's wiring to route data read/write commands addressed to a given faulty primary row/column into a designated redundant row/column. Due to the large amount of embedded memory utilized in modern SoCs, the ability test and replace faulty memory cells with redundant memory cells facilitates manufacturing yields of 90% or higher. However, knowing that memory defects can be fixed by way of utilizing the redundant rows/columns, SoC process designers are more likely to push the process node to the limit (e.g., utilize minimum fabrication process parameters to maximize throughput at the expense of increasing the chance of process-related memory cell defects/faults). Accordingly, memory test processes have become increasingly important to supplement the design-manufacturing process. Before understanding how to test and repair a given embedded memory array, memory test developers must understand the ways in which a faulty memory cell can fail. As used herein, the phrase “faulty memory cell” refers to a memory cell (e.g., a FinFET cell) exhibiting at least one static or dynamic fault that prevents the faulty memory cell from properly storing and retaining a bit value (i.e., either a logic-1 or a logic-0) under all operating conditions. Faulty memory cells are typically produced when localized fabrication process variances generate one or more cell elements (e.g., pull-up or pull-down transistors) that consistently or periodically fail, thereby causing the faulty memory cell to provide erroneous data during operation. Static faults are sensitized (i.e., undesirably affect the logical-0 or logical-1 value stored on the faulty memory cell) by a single read or write operation performed on a given faulty memory cell. An exemplary static fault is a Stuck-At Fault (SAF), wherein the logic state of the faulty memory cell remains constant even when subjected to opposing write operations (e.g., the faulty cell stores a logical-0 even when subjected to a logical-1 write operation). Other well-known static memory faults include Transition Faults (TF), Read Destructive Faults (RDF), Deceptive Read Destructive Faults (DRDF), State Coupling Faults (CFst), Read Destructive Coupling Faults (CFrd), Deceptive Read Destructive Coupling Faults (CFdrd), and Read Disturb Coupling Faults (CFdsr). In contrast to static faults, dynamic faults in faulty memory cell are sensitized by being subjected to a sequence of two or more read or write operations. An exemplary dynamic fault is a dynamic Read Destructive Faults (dRDF), wherein the faulty cell's logic state undesirably changes when subjected to multiple read operations (e.g., the faulty cell switches from logical-0 to logical-1 when subjected to multiple logical-0 read operations). Other well-known dynamic faults include dynamic Deceptive Read Destructive Faults (dDRDF) and dynamic Incorrect Read Faults (dIRF).
A built-in self-test (BIST) circuit is an on-chip diagnosis tool that tests embedded memory, for example, each time an SoC or other IC device is powered-up, periodically during operation, or in response to an external signal or condition. A typical BIST circuit includes a finite state machine (BIST-FSM), an address generator, a data generator, and a programmable test algorithm register (TAR) that are configured to access each associated embedded memory array using techniques known in the art. A BIST test algorithm is the test process executed by the BIST circuit, and typically comprises many elements, referred to as March elements. A March element includes a sequence of operations, for example write-0, write-1, read-0 and read-1, which are applied to each given memory cell before proceeding to a next memory cell. The March element also designates whether the operations proceed from memory cell to memory cell in an increasing order of addresses, or in a decreasing order of addresses, or in some other predefined order of addresses. A sequence of March elements is defined as a March test. As used herein, a notation that describes a given March test is defined as follows. A complete March test is delimited by a ‘{ . . . }’ parenthesis pair whereas a March element is delimited by a ‘( . . . )’ parenthesis pair. A given March element can include a plurality of following operations, with notations as indicated: increase address order notated by ‘’, and decrease address order notated by ‘’. Write logical 0 (write-0), write logical 1 (write-1), read logical 0 (read-0) and read logical 1 (read-1) are notated respectively by ‘W0’, ‘W1’, ‘R0’ and ‘R1’. As an example of notation, the March test {(W0), (R0,W1), (R1,W0)} instructs to write-0 to memory addresses in an increasing address order sequence, then also in the increasing order of addresses read-0 and write-1, and finally in the decreasing order of addresses read-1 and write-0. The BIST circuit TAR holds information relating to the March elements performed by a given memory test algorithm, namely an addressing direction, an addressing type, an operation code (that is, a sequence of read or write operations to be applied to each memory cell) and a pattern type (that is, a code that represents data to be written to the memory cells). Upon triggering of the BIST, the BIST-FSM of the apparatus reads data from the TAR, and thereby selects the addressing direction, the addressing type, the code corresponding to the background data pattern, and the sequence of read or write operations. Based on the pattern type, the data generator generates the test data. Based upon the addressing direction and the addressing type, the address generator selects the memory cell to be tested. Based upon the operation code, the test data is applied to the memory cell to be tested.
The combination of FinFET's unique structure and the evolving fabrication processes currently being developed for each new generation of smaller-feature FinFETs (e.g., 16 nm, 14 nm, 10 nm and 7 nm) provides room for new fault types in FinFET-based memories that may not be anticipated, and therefore not detected by the existing test algorithms used for testing planar-based memories.
What is needed is a testing methodology that reliably detects a wide range of dynamic faults arising in FinFET-based memory arrays. What is particularly needed is a scalable testing method that can be easily modified to detect new dynamic faults that may arise as FinFET cells are fabricated using ever-smaller fabrication process feature sizes.